Hi all,
I found the way to OC my kernel up. That
Code:
/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
unsigned int use_for_scaling;
unsigned int acpuclk_khz;
int pll;
unsigned int acpuclk_src_sel;
unsigned int acpuclk_src_div;
unsigned int ahbclk_khz;
unsigned int ahbclk_div;
unsigned int axiclk_khz;
unsigned int sc_core_src_sel_mask;
unsigned int sc_l_value;
int vdd;
unsigned long lpj; /* loops_per_jiffy */
};
What we have to do is:
1. Declare a new struct, that is copied from defaults like this:
Code:
struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
/* Update AXI_S and PLL0_S macros if above row numbers change. */
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
/*
{ 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
* */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
2. Initialize: do the following changes (the commented out line is the former, the normal is my change)
Code:
/*
* static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;
3. Change static void __init acpu_freq_tbl_fixup(void)
Code:
...
case 0x00:
max_acpu_khz = 1228800;
break;
...
Build it, then you'll done!
My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:
Do you know the relationship between the frequency and loops_per_jiffy?
Recommended VDD value (int vdd) with each value of frequency?
unsigned int sc_core_src_sel_mask;: how do we use it effectively?
For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!
Change list: http://www.mediafire.com/?zc3sg4i912vk681
I found the way myself, seems that noone is interested in such topic!
chacona said:
Hi all,
I found the way to OC my kernel up. That
Code:
/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
unsigned int use_for_scaling;
unsigned int acpuclk_khz;
int pll;
unsigned int acpuclk_src_sel;
unsigned int acpuclk_src_div;
unsigned int ahbclk_khz;
unsigned int ahbclk_div;
unsigned int axiclk_khz;
unsigned int sc_core_src_sel_mask;
unsigned int sc_l_value;
int vdd;
unsigned long lpj; /* loops_per_jiffy */
};
What we have to do is:
1. Declare a new struct, that is copied from defaults like this:
Code:
struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
/* Update AXI_S and PLL0_S macros if above row numbers change. */
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
/*
{ 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
* */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
2. Initialize: do the following changes (the commented out line is the former, the normal is my change)
Code:
/*
* static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;
3. Change static void __init acpu_freq_tbl_fixup(void)
Code:
...
case 0x00:
max_acpu_khz = 1228800;
break;
...
Build it, then you'll done!
My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:
Do you know the relationship between the frequency and loops_per_jiffy?
Recommended VDD value (int vdd) with each value of frequency?
unsigned int sc_core_src_sel_mask;: how do we use it effectively?
For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!
Change list: http://www.mediafire.com/?zc3sg4i912vk681
Click to expand...
Click to collapse
chacona said:
Hi all,
I found the way to OC my kernel up. That
Code:
/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
unsigned int use_for_scaling;
unsigned int acpuclk_khz;
int pll;
unsigned int acpuclk_src_sel;
unsigned int acpuclk_src_div;
unsigned int ahbclk_khz;
unsigned int ahbclk_div;
unsigned int axiclk_khz;
unsigned int sc_core_src_sel_mask;
unsigned int sc_l_value;
int vdd;
unsigned long lpj; /* loops_per_jiffy */
};
What we have to do is:
1. Declare a new struct, that is copied from defaults like this:
Code:
struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
/* Update AXI_S and PLL0_S macros if above row numbers change. */
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
/*
{ 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
* */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
2. Initialize: do the following changes (the commented out line is the former, the normal is my change)
Code:
/*
* static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;
3. Change static void __init acpu_freq_tbl_fixup(void)
Code:
...
case 0x00:
max_acpu_khz = 1228800;
break;
...
Build it, then you'll done!
My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:
Do you know the relationship between the frequency and loops_per_jiffy?
Recommended VDD value (int vdd) with each value of frequency?
unsigned int sc_core_src_sel_mask;: how do we use it effectively?
For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!
Change list: http://www.mediafire.com/?zc3sg4i912vk681
Click to expand...
Click to collapse
Quite interesting!!!!
What does your kernel do apart from overclocking ?
Does it resolve the voice issue in CM 7?
If any advantages kindly suggest
Hi, recently I have to work using C#, so I have no time to investigate more on CM7. With CM7, currently I notice that there are issues regarding keys such as MUTE, CAMERA, and kernel power issues. What is the voice problem with CM7, could you tell me?
chacona said:
Hi, recently I have to work using C#, so I have no time to investigate more on CM7. With CM7, currently I notice that there are issues regarding keys such as MUTE, CAMERA, and kernel power issues. What is the voice problem with CM7, could you tell me?
Click to expand...
Click to collapse
The voice issue is:
Then someone calls and you answer, other person hears a garbeled voice,
But if you disconnect and recall its working fine
prasad12ka4 said:
The voice issue is:
Then someone calls and you answer, other person hears a garbeled voice,
But if you disconnect and recall its working fine
Click to expand...
Click to collapse
Okay, thank you for your information. With the information from The Manii about the Phoenix kernel, I am testing their work to see whether problems in stock kernel are solved or not. I will note this issue to see whether I can fix it. At least, I think we should have a good working kernel first.
hope we could make it work, would be cool to have it at least at 1.4 to 1.9 or even 2ghz
Related
Update 12-19-11
Compatibility fix in CPU table, for non booting devices
1.0.3.5
Flashable zip:http://db.tt/QwfI7iaH
For Developers:http://db.tt/qAuFGoSg
Featuring:
2.6.35.14
GXkernels will be considered experimental, and should be viewed as a work in progress
For use with Gingerbread roms for Dell Streak
1.0.3.1
For flashable zip:http://db.tt/E098hb8X
For Developers:http://db.tt/YenTO0s4
Larger cpu table 245 - 1286.8
Safe recommended settings are 245 - 1045
Potential wifi fix for some users, special thanks DSC-Team
CIFS is included, ipv6 is removed, scsi support in kernel removed.
more voltage work on the table, for those of you interested in GXkernel table
GXkernel flexes through these frequencies-
here it is!
Code:
struct clkctl_acpu_speed acpu_freq_tbl_998[] = {
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 950},
/* Update AXI_S and PLL0_S macros if above row numbers change. */
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 1, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1075},
{ 1, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1100},
{ 1, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1125},
{ 1, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1150},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1175},
{ 1, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1200},
{ 1, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1225},
{ 1, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1250},
{ 1, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1275},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1300},
{ 1, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1325},
{ 1, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1350},
{ 1, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1375},
{ 1, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1375},
{ 1, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1400},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1400},
{ 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1B, 1400},
{ 1, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1C, 1400},
{ 1, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1D, 1425},
{ 1, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1E, 1425},
{ 1, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1F, 1425},
{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x20, 1450},
{ 1, 1262800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x21, 1500},
{ 1, 1286800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x21, 1550},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
1.0
Based on the Dell source 4.05
a modified CPU table which scales through 18 frequencies;
245 to 1152
Voltage is tweaked higher, on higher frequencies, up to 1450
All 18 frequencies select-able
Download links---
For recovery, the flashable zip: http://db.tt/vGRN98hq
For devs: http://db.tt/PR8xaBTJ
Best wishes, and thanks to all Developers and to you the user!
-Greg
Using this kernal on dsc rom. So far so good.
Sent from the SuperStreak! ;-)
borijess said:
Using this kernal on dsc rom. So far so good.
Sent from the SuperStreak! ;-)
Click to expand...
Click to collapse
+1 trying it on DSC 62b. Seems rock solid so far
Another great kernel. Awesome work, thanks Greg!
greg9100 said:
Featuring:
2.6.35.14
GXkernels will be considered experimental, and should be viewed as a work in progress
For use with Gingerbread roms for Dell Streak
Based on the Dell source 4.05
a modified CPU table which scales through 18 frequencies;
245 to 1152
Voltage is tweaked higher, on higher frequencies, up to 1450
All 18 frequencies select-able
Download links---
For recovery, the flashable zip: http://db.tt/vGRN98hq
For devs: http://db.tt/PR8xaBTJ
Best wishes, and thanks to all Developers and to you the user!
-Greg
Click to expand...
Click to collapse
Great work, nice to finally see the overclockable Gkernel, will you be extending the frequency range past 1152mhz?
Does this kernel contain all the tweaks and features from the original gkernel?
Dsc 0.62b rom + GXkernel 1.0 + Overclock.
Good. Nice. Wonderful. Perfect. Great!!
Thank you so much Greg T_T.
My streak is very smooth. Thank you.
sharptv said:
Does this kernel contain all the tweaks and features from the original gkernel?
Click to expand...
Click to collapse
Yes, all tweaks from Gkernels project reside inside GXkernels
(InsertNameHere) said:
Great work, nice to finally see the overclockable Gkernel, will you be extending the frequency range past 1152mhz?
Click to expand...
Click to collapse
I am going to try it!
installed over 0.62b noting same set of max-min frequencies selectable in cpu master pro
add contact not working
dsnreddy said:
add contact not working
Click to expand...
Click to collapse
working for me, whant language r u using?
GXkernel1.0
Working great for me, no issues.
nice kernel, work awesome in mine
questions :
whats the difference between gxkrnel vs gkernel vs sd kernel?
thanks greg, u & your kernel is rock!
All of the changes to Gkernel are included into GXkernel; you can see the list of changes at Gkernels 1st post in the forums,
The main difference from SD kernel is that it is the dell 4.05 source, patched up to 2.6.35.14, including the changes to the .config,
I believe SD kernel to have been made mostly from the Olleh sources(I may be wrong) or possibly from amalgamated sources, probably including a host of tweaks by DJ Steve and or Fards;
The progenitor config was pulled from SD kernel as a base with which to work on, for which I give thanks to DJ Steve, and also for his tip regarding wifi practices-
GXkernel is basically Gkernels project with overclocking-
It has a modified CPU table
I am also still collaborating with DSC-Team on other DSC kernels, you can follow our work on that thread;
-G
Better system responsiveness and at this moment I don't see any problems. Realy like it! Good work!
Can't stand without trying ~~
Hello, I‘ve tried with GS 2.4.4 as HD games use to be too slow and when start a game or a few minutes after got stuck and have to remove battery.
Any explanation? Thank you
greg9100 said:
All of the changes to Gkernel are included into GXkernel; you can see the list of changes at Gkernels 1st post in the forums,
The main difference from SD kernel is that it is the dell 4.05 source, patched up to 2.6.35.14, including the changes to the .config,
I believe SD kernel to have been made mostly from the Olleh sources(I may be wrong) or possibly from amalgamated sources, probably including a host of tweaks by DJ Steve and or Fards;
The progenitor config was pulled from SD kernel as a base with which to work on, for which I give thanks to DJ Steve, and also for his tip regarding wifi practices-
GXkernel is basically Gkernels project with overclocking-
It has a modified CPU table
I am also still collaborating with DSC-Team on other DSC kernels, you can follow our work on that thread;
-G
Click to expand...
Click to collapse
thanks greg, will always excited to use your next project
great job
Does GXKernel have the VPN, CIFS modules ready ?
Also, I'd like to ask, has anyone tried GTA3 on Streak ? (with or without GXKernel)
which version should I try ?
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AOSPA 4.3+ PARANOIDANDROID
Kitkat 4.4.2 KVT49L android-4.4.2_r2.1
Download ROMS from DOWNLOAD HERE
1. DOWNLOAD YOUR ROM
2. DOWNLOAD THE LATEST PA GAPPS PACKAGE - always check/use up to date Gapps unless otherwise noted
http://goo.gl/mYKmfL - RECOMMEND mini modular PA Gapps
or BANKS - if having issues with PA Gapps
Wipe Fresh Clean Install (you all know the procedure)
3. COMPLETE CLEAN WIPE - *includes system*
4. FLASH ROM & GAPPS
5. WIPE CACHE & DALVIK
5. RUN INITIAL SETUP & REBOOT
Let boot take as much time as needed. This will help avoid boot issues.
GIT
GERRIT
FAQ + HELP
BUG TRACKER
COMMUNITY + CHANGELOGS
Disclaimer / Warning!: I'm not responsible for any reason should you bork your phone
Donations
If you want to donate, feel free to do so otherwise don't forget to hit thanks and show your appreciation for all the hard work that goes into this.
My Github Sources
Please stick to development here!!! Take all questions to Q&A thread - thanks Pony Express!!!
RULES
You must read the OP & Installation Instructions before installing this ROM or posting in this thread
If you don't like how I run this thread. Leave. You do not have to be here and you are not forced to read it. You are doing so on your own free will.
Search before posting here. You are most likely not the only one to have the question/issue.
Have fun in this thread. I don't mind if we have some fun, joke around, or whatever. As long as it's fun.
If you're going to post here, keep it to this ROM and this ROM only (unless its fun as mentioned above). It is useless to compare to Stock ROMs, CM10 ROMS, ect...
Please watch the 2 videos provided below before posting in this thread. thanks
Thank g33k3r for TOT file or whoever else involved in getting it.. You can go to HIS THREAD HERE to get the official lg image..
This is an paste from Harsh from his thread here
Well, our cpu are made at some quality standards. We have 4 different quality of cpu for apq8064 from Qualcomm. so depending on which one is on your phone it selects frequency table from slow, nominal, fast and faster.
Google kernel source have same frequency table for fast and faster. So those with faster are not getting their extra advantage
You can identify you CPU chip by below command in terminal.
adb shell dmesg | grep PVS
It will give you some output as given example below
Click to expand...
Click to collapse
Code:
adb shell dmesg | grep PVS
[ 0.873920] acpuclk-8064 acpuclk-8064: ACPU PVS: FAST
And faster binned CPU has lot to do with UV, when you look as frequency table of faster, it is already preconfigured to have lower voltages than fast, and lot lower than slow binned.
Phones with faster binned should have better battery than slower binned phone out of box without any other configuration.
And for UV its already hardcoded and can be adjusted by System Tuner app further. And OC I am not willing to add. ( I don't think there's any gain in running our phones hotter with higher voltages by OC'ing)
Click to expand...
Click to collapse
default voltages for SLOW:
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 950000 },
{ 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 975000 },
{ 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 975000 },
{ 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 1000000 },
{ 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 1000000 },
{ 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1025000 },
{ 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1025000 },
{ 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 1075000 },
{ 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 1075000 },
{ 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1100000 },
{ 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1100000 },
{ 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1125000 },
{ 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1125000 },
{ 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1175000 },
{ 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1175000 },
{ 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1200000 },
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1200000 },
{ 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1225000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1225000 },
{ 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1237500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1237500 },
{ 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1250000 },
default voltages for NORM:
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 900000 },
{ 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 925000 },
{ 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 925000 },
{ 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 950000 },
{ 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 950000 },
{ 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 975000 },
{ 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 975000 },
{ 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 1025000 },
{ 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 1025000 },
{ 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1050000 },
{ 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1050000 },
{ 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1075000 },
{ 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1075000 },
{ 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1125000 },
{ 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1125000 },
{ 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1150000 },
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1150000 },
{ 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1175000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1175000 },
{ 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1187500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1187500 },
{ 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1200000 },
default voltages for FAST & FASTER:
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 850000 },
{ 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 875000 },
{ 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 875000 },
{ 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 900000 },
{ 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 900000 },
{ 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 925000 },
{ 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 925000 },
{ 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 975000 },
{ 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 975000 },
{ 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1000000 },
{ 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1000000 },
{ 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1025000 },
{ 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1025000 },
{ 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1075000 },
{ 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1075000 },
{ 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1100000 },
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1100000 },
{ 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1125000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1125000 },
{ 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1137500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1137500 },
{ 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1150000 },
So glad to see this here, houstonn! Excellent job my friend.
:good: :highfive:
Sent from my Optimus G using xda app-developers app
Agreed. I'm still rocking the 3/29 build haha
Pie Control works fine for me. It only gave me issues when I flashed the build from 4/2
____
Sent from my LG Original Gangsta
And here we go! Comm. take off time!:crying:I'm so happy!!!
Wow for a moment I was confused whether I was looking at N4 forums...
Great work Devs! You guys are awesome!
Sent from my LG-E970 using xda premium
This is awesome, I'm loving it. Thanks to all the devs involved, great work.
Sent from my Optimus G using xda app-developers app
Curious as to why it will not let me lower min frequency. I lower it but it always puts it right back at 1026....killing my battery.
Sent from my Optimus G using xda app-developers app
Look at cpu spy, I think you will find it actually is going below and just not reporting correctly.
Edit: I just looked at cpu spy and you are in fact correct. Holding steady at 1026+...getting great deep sleep though!
Sent from my Optimus G using xda app-developers app
Jank4AU said:
Look at cpu spy, I think you will find it actually is going below and just not reporting correctly.
Edit: I just looked at cpu spy and you are in fact correct. Holding steady at 1026+...getting great deep sleep though!
Sent from my Optimus G using xda app-developers app
Click to expand...
Click to collapse
Deep sleep is good here as well. Seems like it would be amazing if it would allow itself to clock down. Nothing I do will get my settings to persist. Neither in built in performance control or when I tried setcpu.
Sent from my Optimus G using xda app-developers app
pfoxdizzle said:
Deep sleep is good here as well. Seems like it would be amazing if it would allow itself to clock down. Nothing I do will get my settings to persist. Neither in built in performance control or when I tried setcpu.
Sent from my Optimus G using xda app-developers app
Click to expand...
Click to collapse
Blame Google. Its called touch boost
Sent from my Nexus 7 using xda app-developers app
Never heard of this and found nothing on the internet. Would appreciate a pm if you get the chance.
Sent from my Optimus G using xda app-developers app
pfoxdizzle said:
Never heard of this and found nothing on the internet. Would appreciate a pm if you get the chance.
Sent from my Optimus G using xda app-developers app
Click to expand...
Click to collapse
Chad explained it to me. Its built in to boost up the CPU upon touches to prevent lag. Found it in some n4 threads too
Sent from my Nexus 7 using xda app-developers app
It states that this comes with a modded
Faux kernel. Use fauxclock to disable mpdecision and you'll be able to go below 1GHz. Hopefully the intellidemand governor is present or all 4 cores might be forced online by this.
Sent from my LG-E970 using xda premium
pfoxdizzle said:
Deep sleep is good here as well. Seems like it would be amazing if it would allow itself to clock down. Nothing I do will get my settings to persist. Neither in built in performance control or when I tried setcpu.
Sent from my Optimus G using xda app-developers app
Click to expand...
Click to collapse
What governor are you using? After experimenting with it a little, it appears that Conservative is locked to a low of 1026, but the others like Wheatley and OnDemand behave normally...
Jank4AU said:
What governor are you using? After experimenting with it a little, it appears that Conservative is locked to a low of 1026, but the others like Wheatley and OnDemand behave normally...
Click to expand...
Click to collapse
I tried all the governors. Was also sent to the glorious demigod screen after a reboot so reverting back to my CM backup for now.
Sent from my Nexus 4 using xda app-developers app
Hmm idk about this build, but I'm on the 3/29 build and I'm running the interactive governor clocked to a max of 1512 and min of 288
Deep sleep over night was around 7 hours and 35 minutes out of 7 hours and 38 minutes or something.
blenkows said:
Hmm idk about this build, but I'm on the 3/29 build and I'm running the interactive governor clocked to a max of 1512 and min of 288
Deep sleep over night was around 7 hours and 35 minutes out of 7 hours and 38 minutes or something.
Click to expand...
Click to collapse
It goes down to 288. Just a display bug in apps. The phone scales down.
Sent from my Nexus 4 using xda app-developers app
nygfan760 said:
It goes down to 288. Just a display bug in apps. The phone scales down.
Sent from my Nexus 4 using xda app-developers app
Click to expand...
Click to collapse
Edit: I shouldn't be posting here yet. I'm still on the 0404 build and running the 0408 kernel so I don't know if everything is the same kernel-wise. So excuse me while I bow out for a bit until I'm up to date.
Sent from my Optimus G using xda app-developers app
Hi,
I've decided to organize all the photos I've collected from my long trip, including all the photospheres.
I copied them around in my PC, changed some of the colors, cut, paste, etc.
At some point, the ones I messed around with have lost their 3D ability. Meaning, when I put them back into the phone, I can't "look" around when viewing them. Also they don't work in G+.
This one has remained 3D:
http://dl-1.va.us.xda-developers.co....jpg?key=qVU2BJySBpkbZPH2Hr8Rrw&ts=1403444816
Really techy details:
Code:
Name
14 (10.6).jpg
File URI
content://com.android.providers.media.documents/document/image%3A18614
File Path
/storage/emulated/0/DCIM/Camera/14 (10.6).jpg
File Type
image/jpeg
File Size
596KB
Image Size
3119x1008, 3.1M pixels
GPS
40° 30′ 33.472″ S , 172° 44′ 46.078″ E
ICC Profile
EXIF
*** Editable in JPEG at SAVE dialog ***
[ROOT]
ImageWidth: 4864
ImageLength: 1572
Make: 'LGE'
Model: 'Nexus 5'
Orientation: 1
Software: 'Picasa'
DateTime: '2014:02:12 20:01:22'
ExifOffset: 246
GPSInfo: 382
Unknown Tag (0x9003): '2014:01:08 12:38:19'
Unknown Tag (0x9004): '2014:01:08 12:38:19'
Unknown Tag (0x9207): -1
Unknown Tag (0x9208): 0
[EXIF]
PreviewImageStart: 441
PreviewImageLength: 0
ExifVersion: 48, 50, 50, 48
ColorSpace: sRGB
ExifImageWidth: 3119
ExifImageLength: 1008
InteropOffset: 580
ImageUniqueID: '258b5ddc423685a50000000000000000'
[INTEROPERABILITY]
InteroperabilityIndex: 'R98'
InteroperabilityVersion: 48, 49, 48, 48
[GPS]
GPSLatitudeRef: 'S'
GPSLatitude: 40, 30, 33472/1000 (33.472)
GPSLongitudeRef: 'E'
GPSLongitude: 172, 44, 46078/1000 (46.078)
GPSAltitudeRef: 0
GPSTimeStamp: 12, 37, 4
GPSProcessingMethod: ''
GPSDateStamp: '2014:01:08'
[SUB]
Compression: 6
XResolution: 72
YResolution: 72
ResolutionUnit: 2
JpgFromRawStart: 704
JpgFromRawLength: 3132
IPTC
XMP
[GPano]
UsePanoramaViewer: True
ProjectionType: equirectangular
CroppedAreaImageHeightPixels: 1572
CroppedAreaImageWidthPixels: 4864
FullPanoHeightPixels: 2432
FullPanoWidthPixels: 4864
CroppedAreaTopPixels: 574
CroppedAreaLeftPixels: 0
FirstPhotoDate: 2014-01-07T23:36:54.974Z
LastPhotoDate: 2014-01-07T23:37:59.953Z
SourcePhotosCount: 28
PoseHeadingDegrees: 167.0
LargestValidInteriorRectLeft: 0
LargestValidInteriorRectTop: 0
LargestValidInteriorRectWidth: 4864
LargestValidInteriorRectHeight: 1572
[AFltr]
SourceFileUri: file:///storage/emulated/0/DCIM/Camera/NZ/Takaka/.aux/PANO_20140212_200119.jpg
filterstack: {"EXPOSURE":{"Name":"Exposure","Value":"39"},"CONTRAST":{"Name":"Contrast","Value":"5"},"channelsaturation":{"ARGS":[4,0,0,0,0,0,0]}}
This one's lost it:
http://dl-1.va.us.xda-developers.co....jpg?key=5PILX5Bi6A-iIcPdJ3kvPQ&ts=1403444882
Techy details:
Code:
Name
File Type
image/jpeg
File Size
2MB
Image Size
4118x1940, 7.9M pixels
GPS
ICC Profile
EXIF
*** Editable in JPEG at SAVE dialog ***
[ROOT]
ImageWidth: 4118
ImageLength: 1940
Make: 'LGE'
Model: 'Nexus 5'
Orientation: 1
DateTime: '2014:04:06 09:09:17'
ExifOffset: 2198
Padding: 28, -22, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0... (2060)
[EXIF]
DateTimeOriginal: '2014:04:06 08:44:32'
DateTimeDigitized: '2014:04:06 08:44:32'
MeteringMode: -1
LightSource: 0
Padding: 28, -22, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0... (2060)
IPTC
XMP
As you can see, the functioning image has tons of extra information in sections where the malfunctioning one is empty. Is there a way to restore it? And I can't see how it's lost in any process, except for changing a format or manually removing it.
Thanks.
What I need to do oclocking gpu
/* clk,vol,abb,min,max,down stay, time, pm_qos mem,
pm_qos int, pm_qos cpu_kfc_min, pm_qos cpu_egl_max */
static gpu_dvfs_info gpu_dvfs_table_default[] = {
{667, 1168750, 0, 99, 100, 1, 0, 666000, 275000, 897000, 1500000},
{533, 1062500, 0, 98, 99, 1, 0, 559000, 275000, 897000, 1500000},
{350, 900000, 0, 90, 98, 1, 0, 413000, 275000, 507000, 1500000},
{266, 900000, 0, 78, 95, 1, 0, 413000, 275000, 507000, 1500000},
{160, 900000, 0, 10, 20, 1, 0, 413000, 275000, 507000, 1500000},
};
static int mif_min_table[] = {
200000, 273000, 338000, 413000, 559000, 666000,
};
static gpu_attribute gpu_config_attributes[] = {
{GPU_MAX_CLOCK, 667},
{GPU_MAX_CLOCK_LIMIT, 667},
{GPU_MIN_CLOCK, 160},
{GPU_DVFS_START_CLOCK, 160},
{GPU_DVFS_BL_CONFIG_CLOCK, 160},
{GPU_GOVERNOR_TYPE, G3D_DVFS_GOVERNOR_INTERACTIVE},
{GPU_GOVERNOR_START_CLOCK_DEFAULT, 160},
{GPU_GOVERNOR_START_CLOCK_INTERACTIVE, 160},
{GPU_GOVERNOR_START_CLOCK_STATIC, 160},
{GPU_GOVERNOR_START_CLOCK_BOOSTER, 160},
{GPU_GOVERNOR_TABLE_DEFAULT, (uintptr_t)&gpu_dvfs_table_default},
{GPU_GOVERNOR_TABLE_INTERACTIVE, (uintptr_t)&gpu_dvfs_table_default},
{GPU_GOVERNOR_TABLE_STATIC, (uintptr_t)&gpu_dvfs_table_default},
{GPU_GOVERNOR_TABLE_BOOSTER, (uintptr_t)&gpu_dvfs_table_default},
{GPU_GOVERNOR_TABLE_SIZE_DEFAULT, GPU_DVFS_TABLE_LIST_SIZE(gpu_dvfs_table_default)},
{GPU_GOVERNOR_TABLE_SIZE_INTERACTIVE, GPU_DVFS_TABLE_LIST_SIZE(gpu_dvfs_table_default)},
{GPU_GOVERNOR_TABLE_SIZE_STATIC, GPU_DVFS_TABLE_LIST_SIZE(gpu_dvfs_table_default)},
{GPU_GOVERNOR_TABLE_SIZE_BOOSTER, GPU_DVFS_TABLE_LIST_SIZE(gpu_dvfs_table_default)},
{GPU_GOVERNOR_INTERACTIVE_HIGHSPEED_CLOCK, 440},
{GPU_GOVERNOR_INTERACTIVE_HIGHSPEED_LOAD, 95},
{GPU_GOVERNOR_INTERACTIVE_HIGHSPEED_DELAY, 0},
{GPU_DEFAULT_VOLTAGE, 975000},
{GPU_COLD_MINIMUM_VOL, 0},
{GPU_VOLTAGE_OFFSET_MARGIN, 37500},
{GPU_TMU_CONTROL, 0},
{GPU_TEMP_THROTTLING1, 600},
{GPU_TEMP_THROTTLING2, 533},
{GPU_TEMP_THROTTLING3, 440},
{GPU_TEMP_THROTTLING4, 350},
{GPU_TEMP_TRIPPING, 266},
{GPU_POWER_COEFF, 46}, /* all core on param */
{GPU_DVFS_TIME_INTERVAL, 5},
{GPU_DEFAULT_WAKEUP_LOCK, 1},
{GPU_BUS_DEVFREQ, 0},
{GPU_DYNAMIC_ABB, 0},
{GPU_EARLY_CLK_GATING, 0},
{GPU_DVS, 0},
#ifdef MALI_SEC_HWCNT
{GPU_HWCNT_GATHERING, 1},
{GPU_HWCNT_GPR, 1},
{GPU_HWCNT_DUMP_PERIOD, 50}, /* ms */
{GPU_HWCNT_CHOOSE_JM , 0},
{GPU_HWCNT_CHOOSE_SHADER , 0xF8},
{GPU_HWCNT_CHOOSE_TILER , 0},
{GPU_HWCNT_CHOOSE_L3_CACHE , 0},
{GPU_HWCNT_CHOOSE_MMU_L2 , 0},
#endif
{GPU_RUNTIME_PM_DELAY_TIME, 50},
{GPU_DVFS_POLLING_TIME, 30},
{GPU_PERF_GATHERING, 0},
{GPU_PMQOS_INT_DISABLE, 0},
{GPU_PMQOS_MIF_MAX_CLOCK, 666000},
{GPU_PMQOS_MIF_MAX_CLOCK_BASE, 667},
#ifdef CONFIG_EXYNOS_CL_DVFS_G3D
{GPU_CL_DVFS_START_BASE, 600},
#endif
{GPU_DEBUG_LEVEL, DVFS_WARNING},
{GPU_TRACE_LEVEL, TRACE_ALL},
};
Sorry about the english
Hello good evening days or evenings from wherever they are watching this post haha I would like to know if someone can help me with my problem I'm new to this and I think the phone had a hardbrick my bike z xt 1650-03 with android 8 lo I wanted to go back to android 7 and it worked for me then I got an update and when I was updating it turned off and it did not turn on but it did not turn on it does not do anything but if the pc recognizes it when I connect it via usb ... when trying to make a blankflash I get the following error I would appreciate your help excuse the English greetings and again thank you
Code:
**** Log buffer [000001] 2018-09-07_23:03:13 ****
[ -0.000] Opening device: \\.\COM4
[ 0.016] Detecting device
[ 0.047] ...cpu.id = 2375 (0x947)
[ 0.047] ...cpu.sn = 3567941557 (0xd4aa77b5)
[ 0.047] Opening singleimage
[ 0.295] Loading package
[ 0.312] ...filename = singleimage.pkg.xml
[ 0.323] Loading programmer
[ 0.325] ...filename = programmer.elf
[ 0.325] Sending programmer
[ 0.403] Handling things over to programmer
[ 0.406] Identifying storage type
[ 0.406] Waiting for firehose to get ready
[ 36.998] ReadFile() failed, GetLastError()=0
[ 60.682] Could not determine storage type. Assuming eMMC...
[ 60.682] Identifying CPU version
[ 60.682] Waiting for firehose to get ready
[122.434] Waiting for firehose to get ready
[184.168] ...MSM8996 unknown
[184.168] Determining target secure state
[184.168] Waiting for firehose to get ready
[245.909] ...secure = no
[246.081] Initializing storage
[246.081] Waiting for firehose to get ready
[307.842] Configuring device...
[307.842] Waiting for firehose to get ready
[369.566] Waiting for firehose to get ready
[431.265] Waiting for firehose to get ready
[492.969] Waiting for firehose to get ready
[554.681] Initializing storage
[554.697] Waiting for firehose to get ready
[616.378] Configuring device...
[616.378] Waiting for firehose to get ready
[678.056] Waiting for firehose to get ready
[739.760] Waiting for firehose to get ready
[801.467] Waiting for firehose to get ready
[863.175] Waiting for firehose to get ready
[924.859] Configuring device...
[924.859] Waiting for firehose to get ready
[986.568] Waiting for firehose to get ready
[1048.257] Waiting for firehose to get ready
[1109.941] Waiting for firehose to get ready
[1171.626] ERROR: do_package()->do_recipe()->do_configure()->buffer_read()->device_read()->IO error
[1171.626] Check qboot_log.txt for more details
[1171.626] Total time: 1171.626s
[1171.626] There were some hiccups in backup and restore.
[1171.626] Please save the following files and see a Bootloader member.
[1171.626] 1) ./qboot_log.txt
[1171.626] 2) ./backup_0xD4AA77B5_2018-09-07_230719.img
[1171.626]
[1171.626]
[1171.626] qboot version 3.37
[1171.626]
[1171.626] DEVICE {
[1171.626] name = "\\.\COM4",
[1171.626] flags = "0x64",
[1171.626] addr = "0x61FE5C",
[1171.626] sahara.current_mode = "0",
[1171.626] api.buffer = "0x10C9020",
[1171.626] cpu.serial = "3567941557",
[1171.626] cpu.id = "2375",
[1171.626] cpu.sv_sbl = "0",
[1171.626] cpu.name = "MSM8996",
[1171.626] sahara.programmer = "programmer.elf",
[1171.626] module.firehose = "0xD78DD8",
[1171.626] storage.type = "eMMC",
[1171.626] cpu.ver = "0",
[1171.626] cpu.vername = "unknown",
[1171.626] api.bnr = "0xC7C7B8",
[1171.626] }
[1171.626]
[1171.626]
[1171.626] Backup & Restore {
[1171.626] num_entries = 26,
[1171.626] restoring = "false",
[1171.626] restore_error = "not started",
[1171.626] entries[00] = { skipped = 0, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="cid"},
[1171.626] entries[01] = { skipped = 0, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="frp"},
[1171.626] entries[02] = { skipped = 0, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="fsc"},
[1171.626] entries[03] = { skipped = 0, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="fsg"},
[1171.626] entries[04] = { skipped = 0, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="hw"},
[1171.626] entries[05] = { skipped = 0, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="misc"},
[1171.626] entries[06] = { skipped = 0, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="modemst1"},
[1171.626] entries[07] = { skipped = 0, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="modemst2"},
[1171.626] entries[08] = { skipped = 0, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="persist"},
[1171.626] entries[09] = { skipped = 0, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="sp"},
[1171.626] entries[10] = { skipped = 0, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="utags"},
[1171.626] entries[11] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="aboot"},
[1171.626] entries[12] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="cdt"},
[1171.626] entries[13] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="cmnlib"},
[1171.626] entries[14] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="cmnlib64"},
[1171.626] entries[15] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="devcfg"},
[1171.626] entries[16] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="devinfo"},
[1171.626] entries[17] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="dhob"},
[1171.626] entries[18] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="hob"},
[1171.626] entries[19] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="hyp"},
[1171.626] entries[20] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="keymaster"},
[1171.626] entries[21] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="pmic"},
[1171.626] entries[22] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="prov"},
[1171.626] entries[23] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="rpm"},
[1171.626] entries[24] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="tz"},
[1171.626] entries[25] = { skipped = 1, backup_tried = 0, backup_failed = 0, restore_tried = 0, restore_failed = 0, name ="xbl"},
[1171.626] simg = {
[1171.626] filename = "backup_0xD4AA77B5_2018-09-07_230719.img",
[1171.626] entries[00] = { size = 457172, name = "programmer.elf" },
[1171.626] }
[1171.626] }
[1171.626]
**** Log buffer [000001] 2018-09-08_01:28:48 ****
[ 0.000] Opening device: \\.\COM4
[ 0.003] Detecting device
[ 3.008] ERROR: sahara_greet_device()->change_mode()->do_hello()->IO error
[ 3.008] Check qboot_log.txt for more details
[ 3.008] Total time: 3.030s
[ 3.009]
[ 3.009] qboot version 3.37
[ 3.009]
[ 3.009] DEVICE {
[ 3.009] name = "\\.\COM4",
[ 3.009] flags = "0x64",
[ 3.009] addr = "0x61FE5C",
[ 3.009] api.bnr = "0x1A2E58",
[ 3.009] }
[ 3.009]
[ 3.009]
[ 3.009] Backup & Restore {
[ 3.009] num_entries = 0,
[ 3.009] restoring = "false",
[ 3.009] backup_error = "not started",
[ 3.009] restore_error = "not started",
[ 3.009] }
[ 3.009]