[aospa 4.4.2 kvt49l] paranoidandroid 4.3+ GEEB [05/20] - AT&T LG Optimus G

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AOSPA 4.3+ PARANOIDANDROID
Kitkat 4.4.2 KVT49L android-4.4.2_r2.1
Download ROMS from DOWNLOAD HERE
1. DOWNLOAD YOUR ROM
2. DOWNLOAD THE LATEST PA GAPPS PACKAGE - always check/use up to date Gapps unless otherwise noted
http://goo.gl/mYKmfL - RECOMMEND mini modular PA Gapps
or BANKS - if having issues with PA Gapps
Wipe Fresh Clean Install (you all know the procedure)
3. COMPLETE CLEAN WIPE - *includes system*
4. FLASH ROM & GAPPS
5. WIPE CACHE & DALVIK
5. RUN INITIAL SETUP & REBOOT
Let boot take as much time as needed. This will help avoid boot issues.
GIT
GERRIT
FAQ + HELP
BUG TRACKER
COMMUNITY + CHANGELOGS​
Disclaimer / Warning!: I'm not responsible for any reason should you bork your phone
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If you want to donate, feel free to do so otherwise don't forget to hit thanks and show your appreciation for all the hard work that goes into this.
My Github Sources

Please stick to development here!!! Take all questions to Q&A thread - thanks Pony Express!!!
RULES
You must read the OP & Installation Instructions before installing this ROM or posting in this thread
If you don't like how I run this thread. Leave. You do not have to be here and you are not forced to read it. You are doing so on your own free will.
Search before posting here. You are most likely not the only one to have the question/issue.
Have fun in this thread. I don't mind if we have some fun, joke around, or whatever. As long as it's fun.
If you're going to post here, keep it to this ROM and this ROM only (unless its fun as mentioned above). It is useless to compare to Stock ROMs, CM10 ROMS, ect...
Please watch the 2 videos provided below before posting in this thread. thanks
Thank g33k3r for TOT file or whoever else involved in getting it.. You can go to HIS THREAD HERE to get the official lg image..

This is an paste from Harsh from his thread here
Well, our cpu are made at some quality standards. We have 4 different quality of cpu for apq8064 from Qualcomm. so depending on which one is on your phone it selects frequency table from slow, nominal, fast and faster.
Google kernel source have same frequency table for fast and faster. So those with faster are not getting their extra advantage
You can identify you CPU chip by below command in terminal.
adb shell dmesg | grep PVS
It will give you some output as given example below
Click to expand...
Click to collapse
Code:
adb shell dmesg | grep PVS
[ 0.873920] acpuclk-8064 acpuclk-8064: ACPU PVS: FAST
And faster binned CPU has lot to do with UV, when you look as frequency table of faster, it is already preconfigured to have lower voltages than fast, and lot lower than slow binned.
Phones with faster binned should have better battery than slower binned phone out of box without any other configuration.
And for UV its already hardcoded and can be adjusted by System Tuner app further. And OC I am not willing to add. ( I don't think there's any gain in running our phones hotter with higher voltages by OC'ing)
Click to expand...
Click to collapse
default voltages for SLOW:
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 950000 },
{ 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 975000 },
{ 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 975000 },
{ 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 1000000 },
{ 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 1000000 },
{ 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1025000 },
{ 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1025000 },
{ 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 1075000 },
{ 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 1075000 },
{ 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1100000 },
{ 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1100000 },
{ 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1125000 },
{ 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1125000 },
{ 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1175000 },
{ 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1175000 },
{ 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1200000 },
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1200000 },
{ 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1225000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1225000 },
{ 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1237500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1237500 },
{ 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1250000 },
default voltages for NORM:
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 900000 },
{ 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 925000 },
{ 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 925000 },
{ 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 950000 },
{ 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 950000 },
{ 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 975000 },
{ 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 975000 },
{ 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 1025000 },
{ 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 1025000 },
{ 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1050000 },
{ 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1050000 },
{ 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1075000 },
{ 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1075000 },
{ 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1125000 },
{ 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1125000 },
{ 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1150000 },
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1150000 },
{ 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1175000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1175000 },
{ 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1187500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1187500 },
{ 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1200000 },
default voltages for FAST & FASTER:
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 850000 },
{ 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 875000 },
{ 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 875000 },
{ 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 900000 },
{ 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 900000 },
{ 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 925000 },
{ 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 925000 },
{ 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 975000 },
{ 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 975000 },
{ 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1000000 },
{ 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1000000 },
{ 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1025000 },
{ 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1025000 },
{ 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1075000 },
{ 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1075000 },
{ 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1100000 },
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1100000 },
{ 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1125000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1125000 },
{ 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1137500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1137500 },
{ 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1150000 },

So glad to see this here, houstonn! Excellent job my friend.
:good: :highfive:
Sent from my Optimus G using xda app-developers app

Agreed. I'm still rocking the 3/29 build haha
Pie Control works fine for me. It only gave me issues when I flashed the build from 4/2
____
Sent from my LG Original Gangsta

And here we go! Comm. take off time!:crying:I'm so happy!!!

Wow for a moment I was confused whether I was looking at N4 forums...
Great work Devs! You guys are awesome!
Sent from my LG-E970 using xda premium

This is awesome, I'm loving it. Thanks to all the devs involved, great work.
Sent from my Optimus G using xda app-developers app

Curious as to why it will not let me lower min frequency. I lower it but it always puts it right back at 1026....killing my battery.
Sent from my Optimus G using xda app-developers app

Look at cpu spy, I think you will find it actually is going below and just not reporting correctly.
Edit: I just looked at cpu spy and you are in fact correct. Holding steady at 1026+...getting great deep sleep though!
Sent from my Optimus G using xda app-developers app

Jank4AU said:
Look at cpu spy, I think you will find it actually is going below and just not reporting correctly.
Edit: I just looked at cpu spy and you are in fact correct. Holding steady at 1026+...getting great deep sleep though!
Sent from my Optimus G using xda app-developers app
Click to expand...
Click to collapse
Deep sleep is good here as well. Seems like it would be amazing if it would allow itself to clock down. Nothing I do will get my settings to persist. Neither in built in performance control or when I tried setcpu.
Sent from my Optimus G using xda app-developers app

pfoxdizzle said:
Deep sleep is good here as well. Seems like it would be amazing if it would allow itself to clock down. Nothing I do will get my settings to persist. Neither in built in performance control or when I tried setcpu.
Sent from my Optimus G using xda app-developers app
Click to expand...
Click to collapse
Blame Google. Its called touch boost
Sent from my Nexus 7 using xda app-developers app

Never heard of this and found nothing on the internet. Would appreciate a pm if you get the chance.
Sent from my Optimus G using xda app-developers app

pfoxdizzle said:
Never heard of this and found nothing on the internet. Would appreciate a pm if you get the chance.
Sent from my Optimus G using xda app-developers app
Click to expand...
Click to collapse
Chad explained it to me. Its built in to boost up the CPU upon touches to prevent lag. Found it in some n4 threads too
Sent from my Nexus 7 using xda app-developers app

It states that this comes with a modded
Faux kernel. Use fauxclock to disable mpdecision and you'll be able to go below 1GHz. Hopefully the intellidemand governor is present or all 4 cores might be forced online by this.
Sent from my LG-E970 using xda premium

pfoxdizzle said:
Deep sleep is good here as well. Seems like it would be amazing if it would allow itself to clock down. Nothing I do will get my settings to persist. Neither in built in performance control or when I tried setcpu.
Sent from my Optimus G using xda app-developers app
Click to expand...
Click to collapse
What governor are you using? After experimenting with it a little, it appears that Conservative is locked to a low of 1026, but the others like Wheatley and OnDemand behave normally...

Jank4AU said:
What governor are you using? After experimenting with it a little, it appears that Conservative is locked to a low of 1026, but the others like Wheatley and OnDemand behave normally...
Click to expand...
Click to collapse
I tried all the governors. Was also sent to the glorious demigod screen after a reboot so reverting back to my CM backup for now.
Sent from my Nexus 4 using xda app-developers app

Hmm idk about this build, but I'm on the 3/29 build and I'm running the interactive governor clocked to a max of 1512 and min of 288
Deep sleep over night was around 7 hours and 35 minutes out of 7 hours and 38 minutes or something.

blenkows said:
Hmm idk about this build, but I'm on the 3/29 build and I'm running the interactive governor clocked to a max of 1512 and min of 288
Deep sleep over night was around 7 hours and 35 minutes out of 7 hours and 38 minutes or something.
Click to expand...
Click to collapse
It goes down to 288. Just a display bug in apps. The phone scales down.
Sent from my Nexus 4 using xda app-developers app

nygfan760 said:
It goes down to 288. Just a display bug in apps. The phone scales down.
Sent from my Nexus 4 using xda app-developers app
Click to expand...
Click to collapse
Edit: I shouldn't be posting here yet. I'm still on the 0404 build and running the 0408 kernel so I don't know if everything is the same kernel-wise. So excuse me while I bow out for a bit until I'm up to date.
Sent from my Optimus G using xda app-developers app

Related

More on the Radio & Under-volting

So I have no been using a kernel patch that is giving the radio full voltage as opposed to under-volting the phone.
My results are:
Before: -111dB to -101dB with 1-2 ASU
After (same EXACT location) -97dB to -83dB with 10 ASU.
This is literally without moving the phone an inch. I patched it with a boot command so I could go back and forth and it seems to be directly related. If anyone else would like to test,
Cheesebaron has been kind enough to write this up....
http://dl.dropbox.com/u/2991343/zImage
Will this patch overwrite any other values besides getting more juice to the radio on an undervolted kernel?
For instance, if running pershoots oc-uv kernel then applying this patch would it give the benefits of both kernel and radio?
Can you post the patch itself so we can see what you're doing? All you provided is a zImage which will overwrite any kernel currently on the phone.
Yes, patches please...
How about the standby battery life ?
FYI, fastboot boot zImage will not replace/reflash the zImage in the ROM. It just boot and load to the new zImage. Rebooting will use back to original zImage in the ROM.
momentarylapseofreason said:
So I have no been using a kernel patch that is giving the radio full voltage as opposed to under-volting the phone.
Click to expand...
Click to collapse
I wonder what happens if you give it just a "little" more juice
Other than my brain will get fried quicker ...
wonder what effect this has on the SAR value. Harder to test ofc :/
Code:
creating boot image...
creating boot image - 2146304 bytes
downloading 'boot.img'... OKAY
booting... OKAY
** EDIT **
Got stuck on first boot, its ok now...
Kernel: [email protected] #1 (-81 16)
Kernel: [email protected] #1 (-81 16)
Same result on Cyanogen 5.0.7 test2 on desk have not moved, maybe I will test this in a hard reception spot.
nandroid restore?
pls provide patches/source.
thx.
1wayjonny said:
Code:
creating boot image...
creating boot image - 2146304 bytes
downloading 'boot.img'... OKAY
booting... OKAY
** EDIT **
Got stuck on first boot, its ok now...
Kernel: [email protected] #1 (-81 16)
Kernel: [email protected] #1 (-81 16)
Same result on Cyanogen 5.0.7 test2 on desk have not moved, maybe I will test this in a hard reception spot.
Click to expand...
Click to collapse
If it got stuck on boot and you rebooted, the reason you're seeing the same results is because you have the stock kernel again. The command you sent does not FLASH the kernel. It only boots with it.
To all those asking for the patch, it's in the first post
EDIT: Didn't see that you indeed had different kernel numbers
momentarylapseofreason said:
If it got stuck on boot and you rebooted, the reason you're seeing the same results is because you have the stock kernel again. The command you sent does not FLASH the kernel. It only boots with it.
To all those asking for the patch, it's in the first post
Click to expand...
Click to collapse
No they are talking about the uncompiled source files not the Zimage.
Refer to this thread then because I don't have the source
http://forum.cyanogenmod.com/index.php?/topic/3368-power-for-radio/?
Here are the freq tables though....
struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 19200, CCTL(CLK_TCXO, 1), SRC_RAW, 0, 0, 1000 },
{ 128000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 1000 },
{ 245000, CCTL(CLK_MODEM_PLL, 1), SRC_RAW, 0, 0, 1000 },
{ 256000, CCTL(CLK_GLOBAL_PLL, 3), SRC_RAW, 0, 0, 1000 },
{ 384000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0A, 0, 1000 },
{ 422400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0B, 0, 1000 },
{ 460800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0C, 0, 1000 },
{ 499200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0D, 0, 1025 },
{ 537600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0E, 0, 1050},
{ 576000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0F, 0, 1050 },
{ 614400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x10, 0, 1075 },
{ 652800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x11, 0, 1100 },
{ 691200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x12, 0, 1125 },
{ 729600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x13, 0, 1150 },
{ 768000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x14, 0, 1150 },
{ 806400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x15, 0, 1175 },
{ 844800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x16, 0, 1200 },
{ 883200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x17, 0, 1225 },
{ 921600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x18, 0, 1275 },
{ 960000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x19, 0, 1275 },
{ 998400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1A, 0, 1275 },
there is nothing new here. you've just increased the voltages back to shipping stock.
I think that's his point that if under volt then that's where bad reception comes from?
So my question is will this still give us the performance we want from the processor while not juicing our batterys while improving reception..
pershoot said:
there is nothing new here. you've just increased the voltages back to shipping stock.
Click to expand...
Click to collapse
Thank you Captain Obvious. The point is that while we are getting better battery life, we are losing reception. So we can have a fully charged phone that can't make a call. Logical to me?
pistol4413 said:
So my question is will this still give us the performance we want from the processor while not juicing our batterys while improving reception..
Click to expand...
Click to collapse
Eh!? Performance (if you are referring to processing speed) wasn't affected by voltage changes in the way that Cyanogen/pershoot were modding them.
As for "juicing" our batteries, yes, it will take more power to keep the voltages up. I'd much rather have to charge my phone more often than not be able to make a call.
yes I noticed this too with the latest cyan release my signal is crap all the time, now.
momentarylapseofreason said:
Eh!? Performance (if you are referring to processing speed) wasn't affected by voltage changes in the way that Cyanogen/pershoot were modding them.
As for "juicing" our batteries, yes, it will take more power to keep the voltages up. I'd much rather have to charge my phone more often than not be able to make a call.
Click to expand...
Click to collapse
hey i can dig it. i dont mind having to charge more often seeing as i have two batteries.
ianandamy said:
yes I noticed this too with the latest cyan release my signal is crap all the time, now.
Click to expand...
Click to collapse
edit your build.prop
current values:
ro.ril.gprsclass=10
ro.ril.hsxpa=1
new values:
ro.ril.gprsclass=12
ro.ril.hsxpa=2
push back to phone in system directory, reboot
made a huge difference to me - I think I found that info on the cyanogen forums
In fact, my nexus now has better reception than my N96, same mobile provider, same location. And i'm using pershoot kernal currently, latest testing cyanogen

[Q] acpuclock-7x30.c modification wont boot.

hello so recently i decided to compile a custom over-clocked kernel for the mecha the first modification was to change some of the cpu frequency's but after doing so and compiling when i try to boot with the kernel installed my phone just seems to lock up and never boot. the code seems good to me but i figure ill let you all have a look.
Code:
static struct cpufreq_frequency_table freq_table[] = {
{ 0, 250000 },
{ 1, 350000 },
{ 2, 450000 },
{ 3, 550000 },
{ 4, 650000 },
{ 5, 750000 },
{ 6, 850000 },
{ 7, 950000 },
{ 8, 1050000 },
{ 9, 1150000 },
{ 10, 1250000 },
{ 11, 1350000 },
{ 12, 1450000 },
{ 13, 1550000 },
{ 14, 1650000 },
{ 15, 1750000 },
{ 16, 1850000 },
{ 17, 1950000 },
{ 16, CPUFREQ_TABLE_END },
};
/* Use negative numbers for sources that can't be enabled/disabled */
#define SRC_LPXO (-2)
#define SRC_AXI (-1)
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 24576, SRC_LPXO, 0, 0, 30720, 900, VDD_RAW(900) },
{ 61440, PLL_3, 5, 11, 61440, 900, VDD_RAW(900) },
{ 122880, PLL_3, 5, 5, 61440, 900, VDD_RAW(900) },
{ 184320, PLL_3, 5, 4, 61440, 900, VDD_RAW(900) },
{ MAX_AXI_KHZ, SRC_AXI, 1, 0, 61440, 900, VDD_RAW(900) },
{ 250000, PLL_3, 5, 2, 122500, 900, VDD_RAW(900) },
{ 350000, PLL_3, 5, 1, 192000, 950, VDD_RAW(950) },
{ 450000, PLL_1, 2, 0, 192000, 950, VDD_RAW(950) },
{ 550000, PLL_3, 5, 1, 192000, 975, VDD_RAW(975) },
{ 650000, PLL_2, 3, 0, 192000, 1000, VDD_RAW(1000) },
{ 750000, PLL_2, 3, 0, 192000, 1025, VDD_RAW(1025) },
{ 850000, PLL_2, 3, 0, 192000, 1050, VDD_RAW(1050) },
{ 950000, PLL_2, 3, 0, 192000, 1050, VDD_RAW(1050) },
{ 1050000, PLL_2, 3, 0, 192000, 1100, VDD_RAW(1100) },
{ 1150000, PLL_2, 3, 0, 192000, 1150, VDD_RAW(1150) },
{ 1250000, PLL_2, 3, 0, 192000, 1175, VDD_RAW(1175) },
{ 1350000, PLL_2, 3, 0, 192000, 1225, VDD_RAW(1225) },
{ 1450000, PLL_2, 3, 0, 192000, 1300, VDD_RAW(1300) },
{ 1550000, PLL_2, 3, 0, 192000, 1400, VDD_RAW(1400) },
{ 1650000, PLL_2, 3, 0, 192000, 1400, VDD_RAW(1400) },
{ 1750000, PLL_2, 3, 0, 192000, 1450, VDD_RAW(1450) },
{ 1850000, PLL_2, 3, 0, 192000, 1450, VDD_RAW(1450) },
{ 1950000, PLL_2, 3, 0, 192000, 1450, VDD_RAW(1450) },
{ 0 }
};
before I modified this area the kernel booted fine.
the rest of the code is a clone of adrynalyne's master source.
Adryn's new kernel supports changing that information on the fly. Also, why would you want so many frequencies? That would actually make it less effiecent.
I wanted to test certain speeds/voltages on my phone still why won't it boot up the voltages and clock speeds as so.
Sent from my ADR6400L using XDA App

Dell Venue overclocking development!

Hi all,
I found the way to OC my kernel up. That
Code:
/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
unsigned int use_for_scaling;
unsigned int acpuclk_khz;
int pll;
unsigned int acpuclk_src_sel;
unsigned int acpuclk_src_div;
unsigned int ahbclk_khz;
unsigned int ahbclk_div;
unsigned int axiclk_khz;
unsigned int sc_core_src_sel_mask;
unsigned int sc_l_value;
int vdd;
unsigned long lpj; /* loops_per_jiffy */
};
What we have to do is:
1. Declare a new struct, that is copied from defaults like this:
Code:
struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
/* Update AXI_S and PLL0_S macros if above row numbers change. */
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
/*
{ 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
* */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
2. Initialize: do the following changes (the commented out line is the former, the normal is my change)
Code:
/*
* static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;
3. Change static void __init acpu_freq_tbl_fixup(void)
Code:
...
case 0x00:
max_acpu_khz = 1228800;
break;
...
Build it, then you'll done!
My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:
Do you know the relationship between the frequency and loops_per_jiffy?
Recommended VDD value (int vdd) with each value of frequency?
unsigned int sc_core_src_sel_mask;: how do we use it effectively?
For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!
Change list: http://www.mediafire.com/?zc3sg4i912vk681
I found the way myself, seems that noone is interested in such topic!
chacona said:
Hi all,
I found the way to OC my kernel up. That
Code:
/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
unsigned int use_for_scaling;
unsigned int acpuclk_khz;
int pll;
unsigned int acpuclk_src_sel;
unsigned int acpuclk_src_div;
unsigned int ahbclk_khz;
unsigned int ahbclk_div;
unsigned int axiclk_khz;
unsigned int sc_core_src_sel_mask;
unsigned int sc_l_value;
int vdd;
unsigned long lpj; /* loops_per_jiffy */
};
What we have to do is:
1. Declare a new struct, that is copied from defaults like this:
Code:
struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
/* Update AXI_S and PLL0_S macros if above row numbers change. */
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
/*
{ 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
* */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
2. Initialize: do the following changes (the commented out line is the former, the normal is my change)
Code:
/*
* static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;
3. Change static void __init acpu_freq_tbl_fixup(void)
Code:
...
case 0x00:
max_acpu_khz = 1228800;
break;
...
Build it, then you'll done!
My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:
Do you know the relationship between the frequency and loops_per_jiffy?
Recommended VDD value (int vdd) with each value of frequency?
unsigned int sc_core_src_sel_mask;: how do we use it effectively?
For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!
Change list: http://www.mediafire.com/?zc3sg4i912vk681
Click to expand...
Click to collapse
chacona said:
Hi all,
I found the way to OC my kernel up. That
Code:
/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
unsigned int use_for_scaling;
unsigned int acpuclk_khz;
int pll;
unsigned int acpuclk_src_sel;
unsigned int acpuclk_src_div;
unsigned int ahbclk_khz;
unsigned int ahbclk_div;
unsigned int axiclk_khz;
unsigned int sc_core_src_sel_mask;
unsigned int sc_l_value;
int vdd;
unsigned long lpj; /* loops_per_jiffy */
};
What we have to do is:
1. Declare a new struct, that is copied from defaults like this:
Code:
struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
/* Update AXI_S and PLL0_S macros if above row numbers change. */
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
/*
{ 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
* */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
2. Initialize: do the following changes (the commented out line is the former, the normal is my change)
Code:
/*
* static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;
3. Change static void __init acpu_freq_tbl_fixup(void)
Code:
...
case 0x00:
max_acpu_khz = 1228800;
break;
...
Build it, then you'll done!
My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:
Do you know the relationship between the frequency and loops_per_jiffy?
Recommended VDD value (int vdd) with each value of frequency?
unsigned int sc_core_src_sel_mask;: how do we use it effectively?
For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!
Change list: http://www.mediafire.com/?zc3sg4i912vk681
Click to expand...
Click to collapse
Quite interesting!!!!
What does your kernel do apart from overclocking ?
Does it resolve the voice issue in CM 7?
If any advantages kindly suggest
Hi, recently I have to work using C#, so I have no time to investigate more on CM7. With CM7, currently I notice that there are issues regarding keys such as MUTE, CAMERA, and kernel power issues. What is the voice problem with CM7, could you tell me?
chacona said:
Hi, recently I have to work using C#, so I have no time to investigate more on CM7. With CM7, currently I notice that there are issues regarding keys such as MUTE, CAMERA, and kernel power issues. What is the voice problem with CM7, could you tell me?
Click to expand...
Click to collapse
The voice issue is:
Then someone calls and you answer, other person hears a garbeled voice,
But if you disconnect and recall its working fine
prasad12ka4 said:
The voice issue is:
Then someone calls and you answer, other person hears a garbeled voice,
But if you disconnect and recall its working fine
Click to expand...
Click to collapse
Okay, thank you for your information. With the information from The Manii about the Phoenix kernel, I am testing their work to see whether problems in stock kernel are solved or not. I will note this issue to see whether I can fix it. At least, I think we should have a good working kernel first.
hope we could make it work, would be cool to have it at least at 1.4 to 1.9 or even 2ghz

[Q] Braces around scalar initializer for type 'const char*'

Hey all,
I was trying to build CM12 when i got the following error:
Code:
sensors.cpp:80:1: error: braces around scalar initializer for type 'const char*'
};
^
The code affected:
Code:
static const struct sensor_t sSensorList[] = {
{ "BMA22 Acceleration Sensor",
"Bosch",
1, SENSORS_ACCELERATION_HANDLE,
SENSOR_TYPE_ACCELEROMETER, RANGE_A, RESOLUTION_A, 0.2f, 10000, 0, 0, { } },
{ "MS-3C Magnetic Sensor",
"Yamaha",
1, SENSORS_MAGNETIC_FIELD_HANDLE,
SENSOR_TYPE_MAGNETIC_FIELD, RANGE_M, RESOLUTION_M, 4.0f, 10000, 0, 0,{ } },
{ "MS-3C Orientation Sensor",
"Yamaha",
1, SENSORS_ORIENTATION_HANDLE,
SENSOR_TYPE_ORIENTATION, RANGE_O, RESOLUTION_O, 4.2f, 10000, 0, 0, { } },
{ "GP2A Light sensor",
"Sharp",
1, SENSORS_LIGHT_HANDLE,
SENSOR_TYPE_LIGHT, 11000.0f, 1.0f, 0.75f, 0, 0, 0, { } },
{ "GP2A Proximity sensor",
"Sharp",
1, SENSORS_PROXIMITY_HANDLE,
SENSOR_TYPE_PROXIMITY, 5.0f, 5.0f, 0.75f, 0, 0, 0, { } },
};
Can anyone please help?
Cheers!
-Technohacker

how to oc kernel samsung

What I need to do oclocking gpu
/* clk,vol,abb,min,max,down stay, time, pm_qos mem,
pm_qos int, pm_qos cpu_kfc_min, pm_qos cpu_egl_max */
static gpu_dvfs_info gpu_dvfs_table_default[] = {
{667, 1168750, 0, 99, 100, 1, 0, 666000, 275000, 897000, 1500000},
{533, 1062500, 0, 98, 99, 1, 0, 559000, 275000, 897000, 1500000},
{350, 900000, 0, 90, 98, 1, 0, 413000, 275000, 507000, 1500000},
{266, 900000, 0, 78, 95, 1, 0, 413000, 275000, 507000, 1500000},
{160, 900000, 0, 10, 20, 1, 0, 413000, 275000, 507000, 1500000},
};
static int mif_min_table[] = {
200000, 273000, 338000, 413000, 559000, 666000,
};
static gpu_attribute gpu_config_attributes[] = {
{GPU_MAX_CLOCK, 667},
{GPU_MAX_CLOCK_LIMIT, 667},
{GPU_MIN_CLOCK, 160},
{GPU_DVFS_START_CLOCK, 160},
{GPU_DVFS_BL_CONFIG_CLOCK, 160},
{GPU_GOVERNOR_TYPE, G3D_DVFS_GOVERNOR_INTERACTIVE},
{GPU_GOVERNOR_START_CLOCK_DEFAULT, 160},
{GPU_GOVERNOR_START_CLOCK_INTERACTIVE, 160},
{GPU_GOVERNOR_START_CLOCK_STATIC, 160},
{GPU_GOVERNOR_START_CLOCK_BOOSTER, 160},
{GPU_GOVERNOR_TABLE_DEFAULT, (uintptr_t)&gpu_dvfs_table_default},
{GPU_GOVERNOR_TABLE_INTERACTIVE, (uintptr_t)&gpu_dvfs_table_default},
{GPU_GOVERNOR_TABLE_STATIC, (uintptr_t)&gpu_dvfs_table_default},
{GPU_GOVERNOR_TABLE_BOOSTER, (uintptr_t)&gpu_dvfs_table_default},
{GPU_GOVERNOR_TABLE_SIZE_DEFAULT, GPU_DVFS_TABLE_LIST_SIZE(gpu_dvfs_table_default)},
{GPU_GOVERNOR_TABLE_SIZE_INTERACTIVE, GPU_DVFS_TABLE_LIST_SIZE(gpu_dvfs_table_default)},
{GPU_GOVERNOR_TABLE_SIZE_STATIC, GPU_DVFS_TABLE_LIST_SIZE(gpu_dvfs_table_default)},
{GPU_GOVERNOR_TABLE_SIZE_BOOSTER, GPU_DVFS_TABLE_LIST_SIZE(gpu_dvfs_table_default)},
{GPU_GOVERNOR_INTERACTIVE_HIGHSPEED_CLOCK, 440},
{GPU_GOVERNOR_INTERACTIVE_HIGHSPEED_LOAD, 95},
{GPU_GOVERNOR_INTERACTIVE_HIGHSPEED_DELAY, 0},
{GPU_DEFAULT_VOLTAGE, 975000},
{GPU_COLD_MINIMUM_VOL, 0},
{GPU_VOLTAGE_OFFSET_MARGIN, 37500},
{GPU_TMU_CONTROL, 0},
{GPU_TEMP_THROTTLING1, 600},
{GPU_TEMP_THROTTLING2, 533},
{GPU_TEMP_THROTTLING3, 440},
{GPU_TEMP_THROTTLING4, 350},
{GPU_TEMP_TRIPPING, 266},
{GPU_POWER_COEFF, 46}, /* all core on param */
{GPU_DVFS_TIME_INTERVAL, 5},
{GPU_DEFAULT_WAKEUP_LOCK, 1},
{GPU_BUS_DEVFREQ, 0},
{GPU_DYNAMIC_ABB, 0},
{GPU_EARLY_CLK_GATING, 0},
{GPU_DVS, 0},
#ifdef MALI_SEC_HWCNT
{GPU_HWCNT_GATHERING, 1},
{GPU_HWCNT_GPR, 1},
{GPU_HWCNT_DUMP_PERIOD, 50}, /* ms */
{GPU_HWCNT_CHOOSE_JM , 0},
{GPU_HWCNT_CHOOSE_SHADER , 0xF8},
{GPU_HWCNT_CHOOSE_TILER , 0},
{GPU_HWCNT_CHOOSE_L3_CACHE , 0},
{GPU_HWCNT_CHOOSE_MMU_L2 , 0},
#endif
{GPU_RUNTIME_PM_DELAY_TIME, 50},
{GPU_DVFS_POLLING_TIME, 30},
{GPU_PERF_GATHERING, 0},
{GPU_PMQOS_INT_DISABLE, 0},
{GPU_PMQOS_MIF_MAX_CLOCK, 666000},
{GPU_PMQOS_MIF_MAX_CLOCK_BASE, 667},
#ifdef CONFIG_EXYNOS_CL_DVFS_G3D
{GPU_CL_DVFS_START_BASE, 600},
#endif
{GPU_DEBUG_LEVEL, DVFS_WARNING},
{GPU_TRACE_LEVEL, TRACE_ALL},
};
Sorry about the english

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